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Section 1 Overview
1.3
Block Diagram
VCC
VCC
VCC
VCL
VSS
VSS
VSS
VSS
VSS
RES
XTAL
EXTAL
MD2
MD1
NMI
ETRST
PJ0*
PJ1*
PJ2*
PJ3*
PJ4*
PJ5*
PJ6*
PJ7*
PI0*
PI1*
PI2*
PI3*
PI4*
PI5*
PI6*
PI7*
PH0/ExIRQ6/TDPCYI2
PH1/ExIRQ7/TDPCKI2/TDPMCI2
PH2/CIRI
PH3
PH4
PH5
PG0/ExIRQ8/TMIX/TDPCYI1
PG1/ExIRQ9/TMIY/TDPCKI1/TDPMCI1
PG2/ExIRQ10/SDA2
PG3/ExIRQ11/SCL2
PG4/ExIRQ12/ExSDAA
PG5/ExIRQ13/ExSCLA
PG6/ExIRQ14/ExSDAB
PG7/ExIRQ15/ExSCLB
PF0/PWMU0A/IRQ8
PF1/PWMU1A/IRQ9
PF2/TMOY/IRQ10/TDPCYI0
PF3/TMOX/IRQ11/TDPCKI0/TDPMCI0
PF4/PWMU2A
PF5/PWMU3A
PF6/PWMU4A
PF7/PWMU5A
PE0/ExEXCL
1
PE1*
/ETCK
1
PE2*
/ETDI
1
PE3*
/ETDO
1
PE4*
/ETMS
PC0/TIOCA0/WUE8
PC1/TIOCB0/WUE9
PC2/TIOCC0/TCLKA/WUE10
PC3/TIOCD0/TCLKB/WUE11
PC4/TIOCA1/WUE12
PC5/TIOCB1/TCLKC/WUE13
PC6/TIOCA2/WUE14
PC7/TIOCB2/TCLKD/WUE15
Rev. 1.00 Apr. 28, 2008 Page 8 of 994
REJ09B0452-0100
H8S/2600CPU
Clock pulse
generator
ROM
(flasf memory)
2
2
FSI
2
(1 channel)
2
2
2
2
2
SCIF
(1 channel)
2
2
2
2
2
2
Interrupt controller
2
2
8-bit timer
(4 channels)
SCI (2 channels)
Smart Card I/F
(2 channels)
IIC
(3 channels)
10-bit A/D converter
(16 channels)
H-UDI
Port B
Notes: 1. Not supported by the system development tool (emulator)
2. Not supported by TFP-144 V and TLP-145 V
Figure 1.2 Internal Block Diagram
RAM
CIR
(1 channel)
16-bit TCM
(4 channels)
16-bit TDP
(3 channels)
WDT
(2 channels)
PS2
(4 channels)
8-bit PWM
(12 channels)
14-bit PWM
(2 channels)
LPC
(4 channels)
16-bit TPU
(3 channels)
Port 9
Port 8
Port A
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30/LAD0
P31/LAD1
P32/LAD2
P33/LAD3
P34/LFRAME
P35/LRESET
P36/LCLK
P37/SERIRQ
P40/TMI0/TxD2/TCMCYI0
P41/TMO0/RxD2/TCMCKI0/TCMMCI0
P42/SDA1/TCMCYI1
P43/TMI1/SCK2/TCMCKI1/TCMMCI1
P44/TMO1/PWMU2B/TCMCYI2
P45/PWMU3B/TCMCKI2/TCMMCI2
P46/PWX0/PWMU4B/TCMCYI3
P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3
P50/FTxD
P51/FRxD
P52/SCL0
P60/KIN0
P61/KIN1
P62/KIN2
P63/KIN3
P64/KIN4
P65/KIN5
P66/IRQ6/KIN6
P67/IRQ7/KIN7
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
PD0/AN8
PD1/AN9
PD2AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15
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