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Section 9 14-Bit PWM Timer (PWMX)
This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It
can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
9.1
Features
• Division of pulse into multiple base cycles to reduce ripple
• Eight resolution settings
The resolution can be set to 1, 2, 64, 128, 256, 1024, 4096, or 16384 system clock cycles.
• Two base cycle settings
The base cycle can be set equal to T × 64 or T × 256, where T is the resolution.
• Sixteen operation clocks (by combination of eight resolution settings and two base cycle
settings)
Figure 9.1 shows a block diagram of the PWM (D/A) module.
PCSR
Select clock
PWX0
PWX1
Control
logic
[Legend]
DACR:
PWMX D/A control register (6 bits)
DADRA:
PWMX D/A data register A (15 bits)
DADRB:
PWMX D/A data register B (15 bits)
DACNT:
PWMX D/A counter (14 bits)
PCSR:
Peripheral clock select register
Internal clock
φ
φ/2, φ/64, φ/128, φ/256,
φ/1024, φ/4096, φ/16384
Clock
Base cycle compare match A
Fine–adjustment pulse addition A
Base cycle compare match B
Fine–adjustment pulse addition B
Base cycle overflow
Figure 9.1 PWMX (D/A) Block Diagram
Section 9 14-Bit PWM Timer (PWMX)
Comparator A
DADRA
Comparator B
DADRB
DACNT
DACR
Rev. 1.00 Apr. 28, 2008 Page 219 of 994
Internal data bus
Bus interface
Module data bus
REJ09B0452-0100
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