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7.2.3
Port 3
(1)
P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2,
P31/LAD1, P30/LAD0
The pin function is switched as shown below according to the combination of the FSILIE bit in
SLCR of FSI, the SCIFE bit in HICR5 and the LPC4E bit in HICR4 and LPC3E to LPC1E bits in
HICR0 of the LPC, and the P3nDDR bit. LPCENABLE in the following table is expressed by the
following logical expression.
LPCENABLE = 1: FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E
Module
Name
Pin Function
LPC
LPC output
I/O port
P3n output
P3n input
(initial setting)
7.2.4
Port 4
(1)
P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3
The pin function is switched as shown below according to the combination of the PWMX and
PWMU and the P47DDR bit.
Module
Name
Pin Function
PWMX
PWX1 output
PWMU
PWMU5B output
I/O port
P47 output
P47 input
(initial setting)
Logical expression
LPCENABLE
1
0
0
PWMX
PWX1_OE
1
0
0
0
Setting
I/O Port
P3nDDR
1
0
Setting
PWMU
PWMU5B_OE
1
0
Rev. 1.00 Apr. 28, 2008 Page 155 of 994
Section 7 I/O Ports
(n = 7 to 0)
I/O Port
P47DDR
1
1
0
REJ09B0452-0100
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