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Section 9 14-Bit PWM Timer (PWMX)
9.2
Input/Output Pins
Table 9.1 lists the PWMX (D/A) module input and output pins.
Table 9.1
Pin Configuration
Pin Name
PWMX output pin 0
PWMX output pin 1
9.3
Register Descriptions
The PWMX (D/A) module has the following registers. The PWMX (D/A) registers are assigned to
the same addresses with other registers. The registers are selected by the IICE bit in the serial
timer control register (STCR). For details on the module stop control register, see section 26.1.3,
Module Stop Control Registers H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA,
MSTPCRB).
Table 9.2
Register Configuration
Register Name
PWMX (D/A) counter H
PWMX (D/A) counter L
PWMX (D/A) data register AH
PWMX (D/A) data register AL
PWMX (D/A) data register BH
PWMX (D/A) data register BL
PWMX (D/A) control register
Peripheral clock select register PCSR
Notes: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT.
Switching is performed by the REGS bit in DACNT or DADRB.
Upper address: when RELOCATE = 0
*
Lower address: when RELOCATE = 1
Rev. 1.00 Apr. 28, 2008 Page 220 of 994
REJ09B0452-0100
Abbreviation I/O
PWX0
Output
PWX1
Output
Abbreviation R/W
DACNTH
DACNTL
DADRAH
DADRAL
DADRBH
DADRBL
DACR
Function
PWMX output of channel A
PWMX output of channel B
Initial Value Address
R/W
H'00
R/W
H'03
R/W
H'FF
R/W
H'FF
R/W
H'FF
R/W
H'FF
R/W
H'30
R/W
H'00
Data Bus
Width
H'FFA6
8
H'FEA6*
H'FFA7
8
H'FEA7*
H'FFA0
8
H'FEA0*
H'FFA1
8
H'FEA1*
H'FFA6
8
H'FEA6*
H'FFA7
8
H'FEA7*
H'FFA0
8
H'FEA0*
H'FF82
8
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