Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1918

ADSP-SC58x PCIE Register Descriptions
IATU Lower Base Outbound Address Register
The
PCIE_IATU_LBADDR_OUTB_[n]
64 KB. The lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64
KB boundaries. More precisely, the lower 16 bits are zero.
Figure 29-123: PCIE_IATU_LBADDR_OUTB_[n] Register Diagram
Table 29-132: PCIE_IATU_LBADDR_OUTB_[n] Register Fields
Bit No.
(Access)
31:16 VAR
(R/W)
15:0 FIXED
(R/NW)
29–214
register contains the minimum size of an address translation region to
15 14 13 12
0 0 0
FIXED (R)
Lower 16-bits of Address
31 30 29 28
0 0 0
VAR (R/W)
Upper 16 bits of Address
Bit Name
Upper 16 bits of Address.
The PCIE_IATU_LBADDR_OUTB_[n].VAR bit field forms bits [31:16] of the
start address of the address region to be translated. This bit field is writeable.
Lower 16-bits of Address.
The PCIE_IATU_LBADDR_OUTB_[n].FIXED bit field forms bits [15:0] of the
start address of the address region to be translated. The start address must be aligned to
64 KB, so these bits are always 0. A write to this location is ignored by the PCIe core.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
27 26 25 24 23 22 21 20
0 0 0 0 0 0 0 0
Description/Enumeration
4 3 2 1 0
0 0 0 0 0
19 18 17 16
0 0 0 0 0