Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1930

ADSP-SC58x PCIE Register Descriptions
Link Capabilities 2 Register
The
PCIE_LNK_CAPB2_[n]
CRSLNK (R)
Cross Link Support
Figure 29-134: PCIE_LNK_CAPB2_[n] Register Diagram
Table 29-143: PCIE_LNK_CAPB2_[n] Register Fields
Bit No.
(Access)
8 CRSLNK
(R/NW)
7:1 LNKSPDVECT
(R/NW)
29–226
register contains bits that indicate the link speed vector and port cross link status.
15 14 13 12 11 10 9
0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0
Bit Name
Cross Link Support.
When set to 1, the PCIE_LNK_CAPB2_[n].CRSLNK bit indicates that the associ-
ated port supports cross links. When set to 0 on a port that supports link speeds of 8.0
GT/s or higher, this bit indicates that the associated port does not support cross links.
When cleared (=0) on a port that only supports link speeds of 2.5 GT/s or 5.0 GT/s,
this bit provides no information regarding the ports level of cross link support.
Link Speed Vector Support.
The PCIE_LNK_CAPB2_[n].LNKSPDVECT bit field indicates the supported link
speed(s) of the associated port. For each bit, a value of 1 indicates that the correspond-
ing link speed is supported; otherwise, the link speed is not supported.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
8 7 6 5 4 3 2 1
1 0 0 0 0 0 1 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
0 2.5 GT/sec
1 5.0 GT/sec
2 8.0 GT/sec
0
0
LNKSPDVECT (R)
Link Speed Vector Support
0