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Peripherals
Choose DDR Subsystem Register Configuration in the Software Product menu and choose the required
processor this tool takes system information, timing parameters from DDR data sheet, and IO parameters as
inputs and then outputs a header file that the driver uses to program the DDR controller and PHY. The driver
then kicks off the full training sequence.
The SDK will have an integrated configuration file for the device that is on the EVM. If you need a configuration
file for a different device, you need to generate that with the DDR Register Configuration tool.
For more information, see
Subsystem and Device Register configuration.
7.3 Media and Data Storage Interfaces
Media and Data Storage interface support includes 3 x Secure Digital (SD) ((4b+4b+8b) (4-bit SD/SDIO, 8-bit
eMMC)) interface, 1 x General-Purpose Memory Controller (GPMC) and OSPI/QSPI.
For more details, see the Memory Interfaces section in the Peripherals chapter of the device-specific TRM.
7.4 Ethernet Interface Using CPSW3G Common Platform Switch 3-port Gigabit Ethernet
The CPSW3G interface can either be configured as a 3-port switch (interfaces to two external Ethernet ports
(port 1 and 2)) or a dual independent MAC interface having their own MAC address.
CPSW3G support RMII (10/100) or RGMII (10/100/1000). For RMII interface implementation, see the CPSW0
RMII Interface section of the device-specific TRM. TI recommends following the RMII Interface Typical
Application (External Clock Source) described in the device-specific TRM.
CPSW3G allows using mixed RMII/RGMII interface topology.
For more details on the Ethernet interface, see the High-speed Serial Interfaces section in the Peripherals
chapter of the device-specific TRM.
7.5 Programmable Real-Time Unit Subsystem (PRUSS)
Not Supported.
7.6 Universal Serial Bus (USB) Subsystem
AM62A7/AM62A3 processor provides two USB 2.0 Ports. These Ports can be configured as USB host, USB
peripheral, or USB Dual-Role Device (DRD mode). USBn_ID functionality is supported via any of the GPIO.
Follow USB VBUS Design Guidelines section of the device-specific data sheet for scaling the VBUS voltage.
VBUS voltage is required to be connected when the device is configured in device mode. VBUS connection is
optional in host mode.
For USB connections and On-The-Go feature support, see the device-specific TRM.
For more details, see the High-speed Serial Interfaces section in the Peripherals chapter of the device-specific
TRM.
Note the supply requirements when configuring the USB for backup mode.
7.7 General Connectivity
The processor provides multiple instances of UART, Serial Peripheral Interface (SPI), I2C, Multichannel Audio
Serial Port (McASP), Enhanced Pulse Width Modulator (ePWM), Enhanced Quadrature Encoder Pulse (eQEP),
eCAP, CAN with CAN-FD support and GPIOs.
For I2C interface with open drain outputs (MCU_I2C0 and WKUP_I2C0), an external termination (pullup) is
recommended irrespective of peripheral usage.
An external termination (pullup) is recommended for the other I2C interfaces based on the use case. For the
available I2C instances, see the device-specific data sheet.
The number of instances available depends on the application and can be configured using the SysConfig-
PinMux Tool.
For more details, see the Peripherals chapter of the device-specific TRM.
10
Hardware Design Guide for AM62A7/AM62A3 Devices
[FAQ] AM62A7 or AM62A3 Custom board hardware design – Processor DDR
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SPRAD85 – MARCH 2023
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