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M16C/64C Group
16.3.4
DMAC Transfer Cycles
The formula for calculating the number of DMAC transfer cycles is shown below.
Number of transfer cycles per transfer unit = Number of read cycles × j + Number of write cycles × k
Table 16.8
DMAC Transfer Cycles
Transfer Unit
Bus Width
16-bit
(BYTE = low)
8-bit transfers
(DMBIT = 1)
8-bit
(BYTE = high)
16-bit
(BYTE = low)
16-bit transfers
(DMBIT = 0)
8-bit
(BYTE = high)
DMBIT: Bit in the DMiCON register (i = 0 to 3)
Table 16.9
Coefficients j and k (1/2)
Internal ROM, RAM
No waits
inserted
j
1
k
1
Note:
1.
Depends on the set value of the CSE register.
Table 16.10
Coefficients j and k (2/2)
No waits
inserted
j
1
k
2
Note:
1.
Depends on the set values of the CSE register.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Access
Address
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Internal Area
SFR
Wait
one wait
inserted
inserted
2
2
2
2
External Area
Separate bus
one wait inserted
two wait inserted
(1 φ + 1 φ )
2
2
Single-Chip Mode
Number of
Number of
read cycles
write cycles
1
1
1
1
N/A
N/A
N/A
N/A
1
1
2
2
N/A
N/A
N/A
N/A
External Area
Multiplex bus
Wait inserted
one wait
two wait
3
3
(1)
Wait states
three wait inserted
(1 φ + 2 φ )
(1 φ + 3 φ )
3
3
Memory Expansion Mode
Microprocessor Mode
Number of
read cycles
write cycles
1
1
1
1
1
2
2
2
(1)
three wait
3
4
3
4
4
4
Page 246 of 807
16. DMAC
Number of
1
1
1
1
1
2
2
2
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