Detailed Description; Overview; System Cpu - Texas Instruments SimpleLink CC2651R3SIPA Manual

CC2651R3SIPA
SWRS278B – FEBRUARY 2022 – REVISED AUGUST 2023

9 Detailed Description

9.1 Overview

Section 4 shows the core modules of the CC2651R3SIPA device.

9.2 System CPU

The CC2651R3SIPA SimpleLink
application and the higher layers of radio protocol stacks.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
Its features include the following:
• ARMv7-M architecture optimized for small-footprint embedded applications
• Arm Thumb ® -2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm
core in a compact memory size
• Fast code execution permits increased sleep mode time
• Deterministic, high-performance interrupt handling for time-critical applications
• Single-cycle multiply instruction and hardware divide
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
• Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
• Optimized for single-cycle flash memory access
• Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait
states
• Ultra-low-power consumption with integrated sleep modes
• 48 MHz operation
• 1.25 DMIPS per MHz
38 Submit Document Feedback
™
Wireless MCU contains an Arm
Product Folder Links:
® ®
Cortex -M4 system CPU, which runs the
Copyright © 2023 Texas Instruments Incorporated
CC2651R3SIPA
www.ti.com