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RM0453
38.8.6
CPU1 ROM CoreSight peripheral identity register 3 (ROM_PIDR3)
Address offset: 0xFEC
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 REVAND[3:0]: metal fix version
0x0: No metal fix
Bits 3:0 CMOD[3:0]: customer modified
0x0: No customer modifications
38.8.7
CPU1 ROM CoreSight component identity register 0 (ROM_CIDR0)
Address offset: 0xFF0
Reset value: 0x0000 000D
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[7:0]: component ID bits [7:0]
0x0D: Common ID value
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 2
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
REVAND[3:0]
r
r
r
r
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
PREAMBLE[7:0]
r
r
r
r
Debug support (DBG)
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
CMOD[3:0]
r
r
r
r
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
r
r
r
r
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