ST STM32WL55JC Reference Manual page 1378

Debug support (DBG)
AHB-AP
0xE00FF000 0x000
0x004
AP_BASER register
(0xF8)
0x008
0x00C
0x010
0x014
0x018
0xFD0
0xFFC
38.8.1 CPU1 ROM memory type register (ROM_MEMTYPER)
Address offset: 0xFCC
Reset value: 0x0000 0001
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SYSMEM: system memory
1: System memory present on this bus
1378/1454
Figure 390. CPU1 CoreSight topology
CPU1 ROM table
@0xE00FF000
Offset: 0xFFF0F000
Offset: 0xFFF02000
Offset: 0xFFF03000
Offset: 0xFFF01000
Offset: 0xFFF41000
Offset: 0xFFF44000
Top of table
PIDR4
CIDR3
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
System control space (SCS)
@0xE000E000
0x000 Register file base
0xFD0 PIDR4
0xFFC CIDR3
Breakpoint unit (FPB)
@0xE0002000
0x000 Register file base
0xFD0 PIDR4
0xFFC CIDR3
Trace port interface (TPIU)
@0xE0040000
0x000 Register file base
0xFD0 PIDR4
0xFFC CIDR3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. Res. Res.
RM0453 Rev 2
Data watchpoint/trace (DWT)
@0xE0001000
0x000 Register file base
0xFD0 PIDR4
0xFFC CIDR3
Instrumentation trace (ITM)
@0xE0000000
0x000 Register file base
0xFD0 PIDR4
0xFFC CIDR3
Cross trigger (CTI)
@0xE0043000
0x000 Register file base
0xFD0 PIDR4
0xFFC CIDR3
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
Res. Res. Res. Res.
RM0453
MSv60373V2
16
Res.
0
SYSMEM
r