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Debug support (DBG)
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 TRIGINSTATUS[7:0]: trigger input status
There is one bit of the register for each CTITRIGIN input. When a bit is set to 1, it indicates
that the corresponding trigger input is active. When it is set to 0, the corresponding trigger
input is inactive.
CTI trigger out status register (CTI_TRGOSTSR)
Address offset: 0x134
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 TRIGOUTSTATUS[7:0]: trigger output status
There is one bit of the register for each CTITRIGOUT output. When a bit is set to 1, it
indicates that the corresponding trigger output is active. When it is set to 0, the corresponding
trigger output is inactive.
CTI channel in status register (CTI_CHINSTSR)
Address offset: 0x138
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 CHINSTATUS[3:0]: channel input status
There is one bit of the register for each channel input. When a bit is set to 1, it indicates that
the corresponding channel input is active. When it is set to 0, the corresponding channel
input is inactive.
1364/1454
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 2
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
TRIGOUTSTATUS[7:0]
r
r
r
r
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
RM0453
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
r
r
r
r
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
CHINSTATUS[3:0]
r
r
r
r
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