Table 273. Cpu2 Cti Outputs; Table 274. Cpu1 Cti Inputs; Table 275. Cpu1 Cti Outputs - ST STM32WL55JC Reference Manual

RM0453
HALTED
Cortex-M4
HALTED
Cortex-M0+
The steps detailed below force the processors to restart simultaneously:
1. Clear the debug request by writing 0x01, then 0x00, to the CTI_INTACKR register in
each CTI.
2. Cause a pulse on channel 1 by writing 0x02 to the CTI_APPPULSER register in either
CTI. This generates a restart request to both processors.
Note: The debugger can also force both cores to stop simultaneously by writing 0x01 to the
CTI_APPPULSER register in either CTI, which generates a pulse on channel 0.
For more information on the CTI CoreSight component, refer to the Arm
SoC-400 Technical Reference Manual [2].
Figure 389. Cross trigger configuration example
CTI_INENR0 = 0001
Channel 0
CTI M4
CTI_INENR1 = 0000
Channel 1
CTI M4
CTI_INENR0 = 0001
Channel 0
CTI M0+
CTI_INENR1 = 0000
Channel 1
CTI M0+
RM0453 Rev 2
CTI_OUTENR0 = 0001
CTM CTI M0+
CTI_OUTENR1 = 0010
CTM CTI M0+
CTI_OUTENR0 = 0001
CTM CTI M4
CTI_OUTENR1 = 0010
CTM CTI M4
Debug support (DBG)
EDBGRQ
Cortex-M0+
DBGRESTART
Cortex-M0+
EDBGRQ
Cortex-M4
DBGRESTART
Cortex-M4
MSv60371V1
®
CoreSight
1359/1454
1441