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RM0453
CTI lock access register (CTI_LAR)
Address offset: 0xFB0
Reset value: 0x0000 0000
31
30
29
r
r
r
15
14
13
r
r
r
Bits 31:0 ACCESS_W[31:0]: write access enable
Enables write access to some CTI registers by processor cores (debuggers do not need to
unlock the component).
0xC5AC CE55: Write access enabled
Other values: Write access disabled
CTI lock status register (CTI_LSR)
Address offset: 0xFB4
Reset value: 0x0000 0003
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 LOCKTYPE: size of the CTI_LAR register
0: 32 bits
Bit 1 LOCKGRANT: current status of lock.
This bit is always read as zero by an external debugger.
0: Write access permitted
1: Write access blocked (only reads allowed)
Bit 0 LOCKEXIST: lock control mechanism availability
This bit is always read as zero by an external debugger.
0: No lock control mechanism
1: Lock control mechanism implemented
28
27
26
25
r
r
r
r
12
11
10
9
r
r
r
r
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
24
23
22
ACCESS_W[31:16]
r
r
r
8
7
6
ACCESS_W[15:0]
r
r
r
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
RM0453 Rev 2
Debug support (DBG)
21
20
19
18
r
r
r
r
5
4
3
2
r
r
r
r
21
20
19
18
Res.
Res.
Res.
5
4
3
2
LOCK
Res.
Res.
TYPE
r
17
16
r
r
1
0
r
r
17
16
Res.
Res.
1
0
LOCK
LOCK
GRANT
EXIST
r
r
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