Table of Contents
Advertisement
RM0453
38.6.19
DWT CoreSight component identity register 2 (DWT_CIDR2)
Address offset: 0xFF8
Reset value: 0x0000 0005
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[19:12]: component ID bits [23:16]
0x05: Common ID value
38.6.20
DWT CoreSight component identity register 3 (DWT_CIDR3)
Address offset: 0xFFC
Reset value: 0x0000 00B1
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: component ID bits [31:24]
0xB1: Common ID value
38.6.21
DWT register map and reset values
Offset Register name
DWT_CTRLR
0x000
Reset value
DWT_CYCCNTR
0x004
Reset value
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
Table 271. DWT register map and reset values
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
r
r
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
r
r
0
0
0
0
0
0
0
CYCCNT[31:0]
0
0
0
0
0
0
0
0
0
RM0453 Rev 2
Debug support (DBG)
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PREAMBLE[19:12]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PREAMBLE[27:20]
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
r
r
0
0
0
0
0 0
0
0
0
0
0 0
1353/1454
1441
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WL55JC and is the answer not in the manual?