Operation In Event Counter Mode - Renesas 7700 FAMILY User Manual

TIMER A
5.4 Event counter mode

5.4.2 Operation in event counter mode

When the count start bit is set to "1," the counter starts counting of the count source.
The counter counts the count source's valid edges.
When the counter underflows or overflows, the reload register's contents are reloaded and counting
continues.
The timer Ai interrupt request bit is set to "1" when the counter underflows or overflows in
The interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request
bit is cleared to "0" by software.
Figure 5.4.4 shows an example of operation in the event counter mode.
n = Reload register's contents
FFFF
16
n
0000
16
Count start bit "1"
"0"
Up-down bit "1"
"0"
Timer Ai interrupt "1"
request bit
"0"
Note: The above applies when the up-down bit's contents are selected as the up-down switching factor (i.e., up-down
switching factor select bit = "0" ).
Fig. 5.4.4 Example of operation in event counter mode (without pulse output function and two-phase
pulse signal processing function)
5–24
Starts counting.
Set to "1" by software.
Cleared to "0" when interrupt request is accepted or cleared by software.
7751 Group User's Manual
Set to "1" by software.
.
Time