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SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3.5 Method of reception
Figures 7.3.6 and 7.3.7 show initial setting examples for relevant registers when receiving. Reception is
started when all of the following conditions (
satisfy conditions
<Precondition>
The CLK
pin's input is "H" level.
i
Note: When an internal clock is selected, above precondition is ignored.
<Reception conditions>
Reception is enabled (receive enable bit = "1").
Transmission is enabled (transmit enable bit = "1").
Dummy data is present in the UARTi transmit buffer register (transmit buffer empty flag = "0")
When using interrupts, it is necessary to set the relevant register to enable interrupts. For details, refer to
"Chapter 4. INTERRUPTS."
Figure 7.3.8 shows processing after reception's completion.
7–26
to
with the following precondition satisfied.
7751 Group User's Manual
to
) are satisfied. When an external clock is selected,
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