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APPENDIX
Appendix 2. Memory assignment in SFR area
Access characteristics
: It is possible to read the bit state at reading. The written value becomes valid data.
RW
: It is possible to read the bit state at reading. The written value becomes invalid.
RO
: The written value becomes valid data. It is impossible to read the bit state.
WO
: Nothing is assigned. It is impossible to read the bit state. The written value is ignored.
State immediately after a reset
: "0" immediately after a reset.
0
: "1" immediately after a reset.
1
: Undefined immediately after
?
a reset.
Address
20
16
A-D register 0
21
16
22
16
A-D register 1
23
16
24
16
A-D register 2
25
16
26
16
27
16
28
16
29
16
2A
16
2B
16
2C
16
A-D register 6
2D
16
2E
16
2F
16
30
UART0 transmit/receive mode register
16
UART0 baud rate register
31
16
32
16
UART0 transmit buffer register
33
16
34
UART0 transmit/receive control register 0
16
35
UART0 transmit/receive control register 1
16
36
16
UART0 receive buffer register
37
16
38
UART1 transmit/receive mode register
16
39
UART1 baud rate register
16
3A
16
UART1 transmit buffer register
3B
16
3C
UART1 transmit/receive control register 0
16
3D
UART1 transmit/receive control register 1
16
3E
16
UART1 receive buffer register
3F
16
20–6
Register name
b7
A-D register 3
A-D register 4
A-D register 5
A-D register 7
RW
RW
7751 Group User's Manual
0
: Always "0" at reading
: Always undefined at reading
?
0
: "0" immediately after a reset. Fix this bit to "0."
Access characteristics
b0
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
WO
WO
WO
RO
RW
RO
RW
RO
RW
RO
RO
RW
WO
WO
WO
RO
RW
RO
RW
RO
RW
RO
RO
State immediately after a reset
b7
?
0
0
0
0
0
0
?
0
0
0
0
0
0
?
0
0
0
0
0
0
?
0
0
0
0
0
0
?
0
0
0
0
0
0
?
0
0
0
0
0
0
?
0
0
0
0
0
0
?
0
0
0
0
0
0
00
16
?
?
?
0
?
?
?
1
0
0
0
0
0
0
0
?
0
0
0
0
0
0
00
16
?
?
?
0
?
?
?
0
1
0
0
0
0
0
0
?
0
0
0
0
0
0
b0
?
?
?
?
?
?
?
?
0
0
1
0
0
?
0
0
1
0
0
?
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