Renesas 7700 FAMILY User Manual page 172

(1) Interrupt priority level select bits (bits 0 to 2)
These bits select the priority level of the UARTi transmit interrupt or UARTi receive interrupt. When
using UARTi transmit/receive interrupt, select priority levels 1 to 7. When the UARTi transmit/receive
interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL),
so that the requested interrupt is enabled only when its priority level is higher than the IPL. (However,
this applies when the interrupt disable flag (I) = "0.") To disable the UARTi transmit/receive interrupt,
set these bits to "000
(2) Interrupt request bit (bit 3)
The UARTi transmit interrupt request bit is set to "1" when data is transferred from the UARTi
transmit buffer register to the UARTi transmit register. The UARTi receive interrupt request bit is set
to "1" when data is transferred from the UARTi receive register to the UARTi receive buffer register.
However, when an overrun error occurs, it does not change.
Each interrupt request bit is automatically cleared to "0" when its corresponding interrupt request is
accepted. This bit can be set to "1" or "0" by software.
" (level 0).
2
7751 Group User's Manual
SERIAL I/O
7.2 Block description
7–15