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SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3.6 Receive operation
When the receive conditions listed on page 7-26 are satisfied, the UARTi enters the receive enable state.
The receive operations are described below.
The input signal of the RxD
synchronously with the rising of the transfer clock.
The contents of the UARTi receive register are shifted by 1 bit to the right.
Steps
and
are repeated at each rising of the transfer clock.
When 1-byte data is prepared in the UARTi receive register, the contents of this register are transferred
to the UARTi receive buffer register.
Simultaneously with step
request occurs and its interrupt request bit is set to "1."
The receive complete flag is cleared to "0" when the low-order byte of the UARTi receive buffer register
is read out. Figure 7.3.10 shows the receive operation, and Figure 7.3.11 shows an example of receive
timing (when selecting an external clock).
When the transfer format select bit = "1" (MSB first), each bit's position of this register's contents is
reversed and the resultant data is read out.
Fig. 7.3.9 Connection example
7–30
pin is taken into the most significant bit of the UARTi receive register
i
, the receive complete flag is set to "1," and the UARTi receive interrupt
Transmitter side
TxD
i
RxD
i
CLK
i
7751 Group User's Manual
Receiver side
TxD
i
RxD
i
CLK
i
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