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WAIT MODE
11.2 Operation description
11.2.1 Termination by interrupt request occurrence
When an interrupt request occurs, supply of clock
The interrupt request which occurs in
Table 11.2.2 shows the interrupts used to terminate Wait mode.
The occurrence of the watchdog timer interrupt request also terminates Wait mode.
Before executing the WIT instruction, enable interrupts used to terminate Wait mode.
In addition, the interrupt priority level of the interrupt used to terminate Wait mode must be higher than the
processor interrupt priority level (IPL) of the routine where the WIT instruction is executed. When the
multiple interrupts in Table 11.2.2 are enabled, Wait mode is terminated by the first interrupt request.
11.2.2 Termination by hardware reset
The CPU and the SFR area are initialized in the same way as a system reset. However, the internal RAM
area retains the same contents as that before executing the WIT instruction. The termination sequence is
the same as the internal processing sequence which is performed after a reset.
To determine whether a hardware reset was performed to terminate Wait mode or a system reset was
performed, use software after a reset.
Refer to "Chapter 13. RESET" for details about a reset.
11–4
and
CPU
is accepted.
Table 11.2.2 Interrupts used to terminate Wait mode
____
•INT
interrupt (i = 0 to 2)
i
•Timer Ai interrupt (i = 0 to 4)
•Timer Bi interrupt (i = 0 to 2)
•UARTi transmit interrupt (i = 0, 1)
•UARTi receive interrupt (i = 0, 1)
•A-D converter interrupt
Note : Refer to "Chapter 4. INTERRUPTS" and each
functional description about interrupts.
7751 Group User's Manual
starts.
BIU
Interrupt
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