Renesas 7700 FAMILY User Manual page 191

SERIAL I/O
7.3 Clock synchronous serial I/O mode
[Precautions when operating in clock synchronous serial I/O mode]
1. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when
performing only reception, transmit operation (setting for transmission) must be performed. In this case,
dummy data is output from the TxD
2. When receiving, simultaneously set the receive enable bit and the transmit enable bit to "1."
3. When selecting an external clock, satisfy the following 3 conditions with the input to CLK
<When transmitting>
Set the transmit enable bit to "1."
Write transmit data to the UARTi transmit buffer register.
Input "L" level to the
<When receiving>
Set the receive enable bit to "1."
Set the transmit enable bit to "1."
Write dummy data to the UARTi transmit buffer register.
4. When receiving data, write dummy data to the low-order byte of the UARTi transmission buffer register
for each reception of 1-byte data.
5. The output level of the RTS
output level of this pin becomes "H" when receive starts, and it becomes "L" when receive is completed.
The output level of this pin changes regardless of the contents of the transmit enable bit, the transmission
buffer empty flag, and the receive complete flag.
7–34
pin.
i
____
pin (when selecting the
CTS
i
____
pin becomes "L" simultaneously at setting the receive enable bit to "1." The
i
7751 Group User's Manual
____
function).
CTS
pin = "H" level.
i