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Access characteristics
RW
: It is possible to read the bit state at reading. The written value becomes valid data.
: It is possible to read the bit state at reading. The written value becomes invalid.
RO
: The written value becomes valid data. It is impossible to read the bit state.
WO
: Nothing is assigned. It is impossible to read the bit state. The written value is ignored.
State immediately after a reset
: "0" immediately after a reset.
0
: "1" immediately after a reset.
1
: Undefined immediately after
?
a reset.
Address
Register name
40
16
Count start register
41
16
42
One-shot start register
16
43
16
44
16
Up-down register
45
16
46
16
Timer A0 register
47
16
48
16
Timer A1 register
49
16
4A
16
Timer A2 register
4B
16
4C
16
Timer A3 register
4D
16
4E
16
Timer A4 register
4F
16
50
16
Timer B0 register
51
16
52
16
Timer B1 register
53
16
54
16
Timer B2 register
55
16
56
Timer A0 mode register
16
57
Timer A1 mode register
16
58
Timer A2 mode register
16
59
Timer A3 mode register
16
5A
Timer A4 mode register
16
5B
Timer B0 mode register
16
5C
Timer B1 mode register
16
5D
Timer B2 mode register
16
5E
Processor mode register 0
16
5F
Processor mode register 1
16
The access characteristics at addresses 46
(Refer to "Chapter 5. TIMER A.")
The access characteristics at addresses 50
(Refer to "Chapter 6. TIMER B.")
The access characteristics of bit 5 at addresses 5B
mode. (Refer to "Chapter 6. TIMER B.")
The access characteristics of bit 1 at address 5E
to the voltage level supplied to the CNV
Appendix 2. Memory assignment in SFR area
0
: Always "0" at reading
: Always undefined at reading
?
0
: "0" immediately after a reset. Fix this bit to "0."
Access characteristics
b7
RW
WO
WO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
RW
RW
to 4F
varies according to Timer A's operating mode.
16
16
to 55
varies according to Timer B's operating mode.
16
16
to 5D
16
and its state immediately after a reset vary according
16
pin. (Refer to section "2.5 Processor modes.")
SS
7751 Group User's Manual
APPENDIX
State immediately after a reset
b0
b7
00
0
?
0
0
0
0
00
00
00
00
00
0
0
?
?
0
0
?
?
0
0
?
?
0
0
0
0
RW
0
0
0
0
varies according to Timer B's operating
16
b0
16
?
0
0
0
0
?
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
16
16
16
16
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
20–7
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