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TIMER A
5.4 Event counter mode
5.4.1 Setting for event counter mode
Figures 5.4.2 and 5.4.3 show an initial setting example for registers relevant to the event counter mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to "Chapter 4. INTERRUPTS."
Setting up–down register
b7
Setting divide ratio
(b15)
b7
Fig. 5.4.2 Initial setting example for registers relevant to event counter mode (1)
5–22
Selecting event counter mode and each function
b7
b0
0
0 1
Selection of event counter mode
Pulse output function select bit
Count polarity select bit
Up-down switching factor select bit
b0
Up–down register (Address 44
Timer A0 up–down bit
Timer A1 up–down bit
Timer A2 up–down bit
Timer A3 up–down bit
Timer A4 up–down bit
Timer A2 two–phase pulse signal processing select bit
Timer A3 two–phase pulse signal processing select bit
Timer A4 two–phase pulse signal processing select bit
(b8)
b0
b7
Continue to Figure 5.4.3 on next page.
7751 Group User's Manual
Timer Ai mode register (i = 0 to 4)
(Addresses 56
to 5A
)
16
16
0: No pulse output
1: Pulse output
0: Counts at falling edge of external signal.
1: Counts at rising edge of external signal.
0: Contents of up-down register
1: Input signal to TAi
pin
OUT
: It may be either "0" or "1."
)
16
Set the corresponding up–down bit when the contents of
the up down register are selected as the up down
–
switching factor.
0: Down–count
1: Up–count
Set the corresponding bit to "1" when the two–phase pulse
signal processing function is selected for timers A2 to A4.
0: Two–phase pulse signal processing
function disabled
1: Two–phase pulse signal processing
function enabled
Timer A0 register (Addresses 47
Timer A1 register (Addresses 49
b0
Timer A2 register (Addresses 4B
Timer A3 register (Addresses 4D
Timer A4 register (Addresses 4F
"
"
"
Can be set to
0000
to
FFFF
16
16
The counter divides the count source frequency by n + 1
when down-counting, or by FFFF
counting.
–
, 46
16
16
, 48
16
16
, 4A
16
16
, 4C
16
16
, 4E
16
16
"
(n).
– n + 1 when up-
16
)
)
)
)
)
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