Single-Chip Mode - Renesas 7700 FAMILY User Manual

ELECTRICAL CHARACTERISTICS

15.7 Single-chip mode

15.7 Single-chip mode
Timing requirements (V
Symbol
t External clock input cycle time
c
t External clock input high-level pulse width
w(H)
t External clock input low-level pulse width
w(L)
t External clock rise time
r
t External clock fall time
f
t Port P0 input setup time
su(P0D–E)
t Port P1 input setup time
su(P1D–E)
t Port P2 input setup time
su(P2D–E)
t Port P3 input setup time
su(P3D–E)
t Port P4 input setup time
su(P4D–E)
t Port P5 input setup time
su(P5D–E)
t Port P6 input setup time
su(P6D–E)
t Port P7 input setup time
su(P7D–E)
t Port P8 input setup time
su(P8D–E)
t Port P0 input hold time
h(E–P0D)
t Port P1 input hold time
h(E–P1D)
t Port P2 input hold time
h(E–P2D)
t Port P3 input hold time
h(E–P3D)
t Port P4 input hold time
h(E–P4D)
t Port P5 input hold time
h(E–P5D)
t Port P6 input hold time
h(E–P6D)
t Port P7 input hold time
h(E–P7D)
t Port P8 input hold time
h(E–P8D)
Switching characteristics (V
Symbol
t
Port P0 data output delay time
d(E–P0Q)
t
Port P1 data output delay time
d(E–P1Q)
t
Port P2 data output delay time
d(E–P2Q)
t
Port P3 data output delay time
d(E–P3Q)
t
Port P4 data output delay time
d(E–P4Q)
t
Port P5 data output delay time
d(E–P5Q)
t
Port P6 data output delay time
d(E–P6Q)
t
Port P7 data output delay time
d(E–P7Q)
t
Port P8 data output delay time
d(E–P8Q)
Note: For test conditions, refer to Figure 15.15.1.
15–16
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
= 5 V±10%, V
CC SS
Parameter
= 5 V±10%, V
CC
Parameter
7751 Group User's Manual
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
SS
Limits
Unit
Max.
Min.
ns
25
ns
t /2–8
c
ns
t /2–8
c
ns
8
8 ns
ns
60
ns
60
ns
60
ns
60
ns
60
ns
60
ns
60
ns
60
ns
60
ns
0
ns
0
ns
0
ns
0
ns
0
ns
0
ns
0
ns
0
ns
0
Limits
Unit
Min. Max.
ns
60
ns
60
ns
60
ns
60
ns
60
ns
60
ns
60
ns
60
ns
60