Renesas 7700 FAMILY User Manual page 431

FLASH MEMORY VERSION
19.1 Parallel input/output mode
Erase command
Figure 19.1.7 shows the erase command and the erase verify command execution timing.
The command code is latched into the internal command latch at the rising edge of the WE signal
by inputting the control signals and the command code "20
The command code is latched into the internal command latch again at the rising edge of the WE
signal by inputting the control signals and the command code "20
The erase operation is started at the rising edge of the WE signal in the second cycle, and the
built–in flash memory contents are collectively erased within 9.5 ms as measured by the internal
timer.
Write "00 " to all the built–in flash memory area before executing the erase command.
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Note: Be sure to execute a erase verify command after executing the erase command. If this
verification fails, execute repeatedly the erase command and the erase verify command until
the verification passes. (Refer to "19.1.6 Program/erase algorithm flow chart.")
When executing again the erase command after executing the erase verify command and
the verification fails, there is no need to write "00
Erase verify command
This command is executed to verify whether or not all contents of the built–in flash memory have
been erased after executing the erase command.
The address is latched internally at the falling edge of the WE signal by inputting the address, the
control signals, and the command code "A0
the internal command latch at the rising edge of the WE signal.
The data of the specified address (input address) is output to an external by inputting the control
signals in the second cycle.
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" in the first cycle. The command code is latched into
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7751 Group User's Manual
" in the first cycle.
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" again in the second cycle.
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" to the built–in flash memory.
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