Table of Contents
Advertisement
7.2 Block description
Figure 7.2.1 shows the block diagram of Serial I/O. Registers relevant to Serial I/O are described below.
RxD
i
BRG count source
select bits
f
/f
2
4
f
/f
16
32
f
/f
64
128
f
/f
512
1024
CLK
i
CTS
/ RTS
i
i
n: Values set in UARTi baud rate register (BRGi)
Fig. 7.2.1 Block diagram of Serial I/O
1/16
synchronous
BRGi
1 / (n+1)
1/16
synchronous
Clock synchronous
(internal clock selected)
1/2
Clock synchronous
Clock synchronous
(internal clock selected)
(external clock selected)
7751 Group User's Manual
0
0
0
0
0
UART
Receive
Clock
control circuit
UART
Transmit control
Clock
circuit
SERIAL I/O
7.2 Block description
Data bus (odd)
Data bus (even)
Bit converter
D
D
D
D
D
D
D
D
D
0
0
8
7
6
5
4
3
2
1
0
UARTi receive register
Transfer clock
Transfer clock
UARTi transmit register
D
D
D
D
D
D
D
D
D
8
7
6
5
4
3
2
1
0
Bit converter
Data bus (odd)
Data bus (even)
UARTi receive
buffer register
TxD
i
UARTi transmit
buffer register
7–3
Advertisement
Table of Contents
