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<When reading>
E, OE
A
–A
0
14
D
–D
0
7
S
External RAM
data output
<When writing>
E, OE
A
–A
0
14
D
–D
0
7
WE
S
Fig. 17.1.22 Timing chart for SRAM expansion example (minimum model at low-speed running)
12 (min.)
5 (max.)
(A)
t
su
(P0A/P1A/P2A-P1D/P2D) = 135
AC32 (t
)
PHL
t
a
(AD)
t
35 (max.)
(A)
AC32 (t
)
PHL
AC32 (t
)
PHL
7751 Group User's Manual
APPLICATIONS
17.1 Memory expansion
135 (min.)
A
t
a
(S)
D
t
a
(OE)
su
(P2D-E)
135 (min.)
A
D
≥ 30
t
su
(D)
18 (min.)
(A)
AC32 (t
)
PLH
15 (max.)
(Kit guaranteed)
≥ 30
A
18 (min.)
(A)
AC32 (t
)
PLH
AC32 (t
)
PLH
(Unit : ns)
17–27
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