Process On Detecting Overrun Error - Renesas 7700 FAMILY User Manual

7.3.7 Process on detecting overrun error

In the clock synchronous serial I/O mode, an overrun error can be detected.
An overrun error occurs when the next data is prepared in the UARTi receive register with the receive
complete flag = "1" (data is present in the UARTi receive buffer register) and that is transferred to the
receive buffer register, in other words, when the next data is prepared before reading out the contents of
the UARTi receive buffer register. When an overrun error occurs, the next receive data is written into the
UARTi receive buffer register, and the UARTi receive interrupt request bit is not changed.
An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive
buffer register and the overrun error flag is set to "1." The overrun error flag is cleared to "0" by clearing
the receive enable bit to "0."
When an overrun error occurs during reception, initialize the overrun error flag and the UARTi receive
buffer register before performing reception again. When it is necessary to perform retransmission owing to
an overrun error which occurs in the receiver side, set the UARTi transmit buffer register again before
starting transmission again.
The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer
register again are described below.
(1) Method of initializing UARTi receive buffer register
Clear the receive enable bit to "0" (reception disabled).
Set the receive enable bit to "1" again (reception enabled).
(2) Method of setting UARTi transmit buffer register again
Clear the serial I/O mode select bits to "000
Set the serial I/O mode select bits to "001
Set the transmit enable bit to "1" (transmission enabled), and set the transmit data to the UARTi
transmit buffer register.
7.3 Clock synchronous serial I/O mode
" (serial I/O ignored).
2
" again.
2
7751 Group User's Manual
SERIAL I/O
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