Renesas 7700 FAMILY User Manual page 186

[When not using interrupts]
Checking completion of reception
UART0 transmit/receive control register 1 (Address 35
UART1 transmit/receive control register 1 (Address 3D
b7
Reading of receive data
UART0 receive buffer register (Address 36
UART1 receive buffer register (Address 3E
b7
Checking error
UART0 transmit/receive control register 1 (Address 35
UART1 transmit/receive control register 1 (Address 3D
b7
Processing after reading out receive data
Fig. 7.3.8 Processing after reception's completion
b0
1 1
Receive complete flag
0: Reception not completed
1: Reception completed
)
16
)
16
b0
Read out receive data.
16
16
b0
1 1
Overrun error flag
0: No overrun error
1: Overrun error detected
7751 Group User's Manual
7.3 Clock synchronous serial I/O mode
)
16
)
16
)
)
Note : This figure shows the bits and registers required
for processing.
Refer to Figure 7.3.11 about the change of flag
state and the occurrence timing of an interrupt
request.
SERIAL I/O
[When using interrupts]
The UARTi receive interrupt request
occurs when reception is completed.
UARTi receive interrupt
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