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11.1 Clock generating circuit .................................................................................................. 11-2
11.2 Operation description ...................................................................................................... 11-3
11.2.1 Termination by interrupt request occurrence ......................................................... 11-4
11.2.2 Termination by hardware reset ................................................................................ 11-4
11.3 Precautions for Wait mode ............................................................................................. 11-5
CHAPTER 12. CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices ...................................................... 12-2
12.1.1 Descriptions of signals .............................................................................................. 12-2
12.1.2 Operation of bus interface unit (BIU) ..................................................................... 12-8
12.2 Bus cycle .......................................................................................................................... 12-11
12.3 Ready function ................................................................................................................ 12-14
12.3.1 Operation description .............................................................................................. 12-15
12.4 Hold function ................................................................................................................... 12-18
12.4.1 Operation description .............................................................................................. 12-19
13.1 Hardware reset .................................................................................................................. 13-2
13.1.1 Pin state ..................................................................................................................... 13-3
13.1.2 State of CPU, SFR area, and internal RAM area................................................. 13-4
13.1.3 Internal processing sequence after reset ............................................................... 13-9
13.1.4 Time supplying "L" level to RESET pin ................................................................ 13-10
13.2 Software reset .................................................................................................................. 13-12
CHAPTER 14. CLOCK GENERATING CIRCUIT
14.1 Oscillation circuit example ............................................................................................. 14-2
14.1.1 Connection example using resonator/oscillator ...................................................... 14-2
14.1.2 Input example of externally generated clock ......................................................... 14-2
14.2 Clock .................................................................................................................................... 14-3
14.2.1 Clock generated in clock generating circuit ........................................................... 14-4
14.2.2 Operation clock for internal peripheral devices ..................................................... 14-5
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7751 Group User's Manual
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