Renesas 7700 FAMILY User Manual page 33

CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
(4) Bus control
To perform the above operations (1) to (3), the BIU inputs and outputs the control signals, and
controls the address bus and the data bus. The cycle in which the BIU controls the bus and accesses
the memory•I/O device is called the bus cycle. Table 2.2.2 shows the bus cycle at accessing the
internal area.
Refer to "Chapter 12. CONNECTION WITH EXTERNAL DEVICES" about the bus cycle at accessing
the external devices.
Table 2.2.2 Bus cycle at accessing internal area
In low-speed running (f(X
RAM
Internal address bus
Internal data bus
ROM
SFR
2–14
) ≤ 25 MHz)
IN
1 bus cycle = 2
E
Address
Data
7751 Group User's Manual
In high-speed running (f(X
1 bus cycle = 2
E
Internal address bus
Internal data bus
1 bus cycle = 3
E
Internal address bus
Internal data bus
) ≤ 40 MHz)
IN
Address
Data
Address
Data