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15.11 Memory expansion mode and microprocessor mode : When 3- φ access in high-speed running
15.11 Memory expansion mode and microprocessor mode : When 3- φ access in high-speed running
Timing requirements (V
Symbol
t
External clock input cycle time
c
t
External clock input high-level pulse width
w(H)
t
External clock input low-level pulse width
w(L)
t
External clock rise time
r
t
External clock fall time
f
t
Port P1 input setup time
su(P1D–E)
t
Port P2 input setup time
su(P2D–E)
t
Port P4 input setup time
su(P4D–E)
t
Port P5 input setup time
su(P5D–E)
t
Port P6 input setup time
su(P6D–E)
t
Port P7 input setup time
su(P7D–E)
t
Port P8 input setup time
su(P8D–E)
t
Port P1 input hold time
h(E–P1D)
t
Port P2 input hold time
h(E–P2D)
t
Port P4 input hold time
h(E–P4D)
t
Port P5 input hold time
h(E–P5D)
t
Port P6 input hold time
h(E–P6D)
t
Port P7 input hold time
h(E–P7D)
t
Port P8 input hold time
h(E–P8D)
t
Port Pi data setup time with address stabilized
su(P0A/P1A/P2A–P1D/P2D)
ELECTRICAL CHARACTERISTICS
= 0 V, Ta = –20 to 85 °C, f(X
= 5 V±10%, V
CC
SS
Parameter
7751 Group User's Manual
) = 40 MHz, unless otherwise noted)
IN
Data formula
(Max.)
Min.
t
c
t
c
9
5
10
–75
f(X
)
IN
Limits
Unit
Max.
25
ns
/2–8
ns
/2–8
ns
ns
8
ns
8
ns
30
30
ns
60
ns
60
ns
ns
60
ns
60
60
ns
ns
0
0
ns
0
ns
0
ns
ns
0
0
ns
0
ns
ns
50
15–33
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