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7.4.6 Receive operation
When the receive enable bit is set to "1," the UARTi enters the reception enabled state and reception starts
at detecting ST. The receive operation is described below.
The input signal of the RxD
synchronously with the transfer clock's rising.
The contents of UARTi receive register are shifted by 1 bit to the right.
Steps
and
are repeated at each rising of the transfer clock.
When one set of data has been prepared, in other words, the shift according to the selected data format
has been completed; the UARTi receive register's contents are transferred to the UARTi receive buffer
register.
Simultaneously with step
request occurs and its interrupt request bit is set to "1."
The receive complete flag is cleared to "0" when the low-order byte of the UARTi receive buffer register
is read out. Figure 7.4.11 shows an example of receive timing when the transfer data length is 8 bits.
Fig. 7.4.10 Connection example
7.4 Clock asynchronous serial I/O (UART) mode
pin is taken into the most significant bit of the UARTi receive register
i
, the receive complete flag is set to "1," and the UARTi receive interrupt
Transmitter side
TxD
i
RxD
i
7751 Group User's Manual
SERIAL I/O
Receiver side
TxD
i
RxD
i
7–49
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