Renesas 7700 FAMILY User Manual page 189

SERIAL I/O
7.3 Clock synchronous serial I/O mode
"1"
Receive enable bit
"0"
"1"
Transmit enable bit
"0"
"1"
Transmit buffer
empty flag
"0"
"H"
RTS
i
"L"
CLK
i
RxD
i
"1"
Receive complete flag
"0"
"1"
UARTi receive
interrupt request bit
"0"
The above timing diagram applies to the following
setting conditions:
External clock selected.
RTS function selected.
f : Frequency of external clock
EXT
Fig. 7.3.11 Example of receive timing (when selecting external clock)
7–32
Dummy data is set to UARTi transmit buffer register.
1/f
Received data taken in
D D D D D
0 1 2 3 4
UARTi receive register → UARTi receive buffer register
7751 Group User's Manual
UARTi transmit register¨← UARTi transmit buffer register
EXT
D D D D D D
5 6 7 0 1 2
UARTi receive buffer register is read out.
Cleared to "0" when interrupt request is accepted or
cleared by software.
: When the CLKi pin's input level is "H," satisfy the
following cinditions:
Transmit enable bit → "1"
Receive enable bit → "1"
Writing of dummy data to UARTi transmit
buffer register
D D D
3 4 5