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APPLICATIONS
17.1 Memory expansion
17.1 Memory expansion
This section shows examples for memory and I/O expansion. Refer to "Chapter 12. CONNECTION WITH
EXTERNAL DEVICES" for details about the functions and operation of used pins when expanding a memory
or I/O. Refer to "Chapter 15. ELECTRICAL CHARACTERISTICS" for timing requirements of the microcomputer.
Application shown here are just examples. The user shall modify them according to the actual application
and test them.
17.1.1 Memory expansion model
Memory expansion to the external is possible in the memory expansion mode or the microprocessor mode.
The level of the external data bus width select signal makes it possible to select the four memory expansion
models shown in Table 17.1.1.
(1) Minimum model
This is an expansion model of which external data bus width is 8 bits and accessible area is
expanded up to 64 Kbytes. It is unnecessary to connect the address latch externally. This is an
expansion model which is suited to having priority the cost when connecting the memory of which
external data bus width is 8 bits.
(2) Medium model A
This is an expansion model of which external data bus width is 8 bits and accessible area is
expanded up to 16 Mbytes. In this expansion model, the high-order 8 bits of the external address bus
) are multiplexed with the external data bus. Therefore, an n-bit (n ≤ 8) address latch is
(A
to A
23
16
required for latching address (n bits of A
(3) Medium model B
This is an expansion model of which external data bus width is 16 bits and accessible area is
expanded up to 64 Kbytes. This expansion model is used when having priority the rate performance.
In this expansion model, the middle-order 8 bits of the external address bus (A
with the external data bus. Therefore, an 8-bit address latch is required for latching address (A
A
).
8
(4) Maximum model
This is an expansion model of which external data bus width is 16 bits and accessible area is
expanded up to 16 Mbytes. In this expansion model, the high- and middle-order 16 bits of the
external address bus (A
address latch for latching A
are required.
17–2
to A
23
to A
) are multiplexed with the external data bus. Therefore, an 8-bit
23
8
and an n-bit (n ≤ 8) address latch for latching n bits of A
to A
15
8
7751 Group User's Manual
).
16
to A
) are multiplexed
15
8
to
15
to A
23
16
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