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SFR area (0
16
: It is possible to read the bit state at reading. The written value becomes valid data.
RW
: It is possible to read the bit state at reading. The written value becomes invalid.
RO
: The written value becomes valid data. It is not possible to read the bit state.
WO
: Nothing is assigned. It is not possible to read the bit state. The written value becomes invalid.
0 : "0" immediately after a reset.
1 : "1" immediately after a reset.
? : Undefined immediately after
a reset.
Address
Register name
0
16
1
16
2
Port P0 register
16
3
Port P1 register
16
4
Port P0 direction register
16
5
Port P1 direction register
16
6
Port P2 register
16
7
Port P3 register
16
8
Port P2 direction register
16
9
Port P3 direction register
16
A
Port P4 register
16
B
Port P5 register
16
C
Port P4 direction register
16
D
Port P5 direction register
16
E
Port P6 register
16
F
Port P7 register
16
10
Port P6 direction register
16
11
Port P7 direction register
16
12
Port P8 register
16
13
16
14
Port P8 direction register
16
15
16
16
16
17
16
18
16
19
16
1A
16
1B
16
1C
16
1D
16
1E
A-D control register 0
16
1F
A-D control register 1
16
Fig. 13.1.3 State of SFR and internal RAM areas immediately after reset (1)
to 7F
)
16
0
: Always "0" at reading.
: Always undefined at reading.
?
0
0
: "0" immediately after a reset. Fix to "0."
(Do not write "1" into this.)
Access characteristics
b7
@
7751 Group User's Manual
State immediately after a reset
b0
b7
RW
RW
RW
RW
RW
RW
0
RW
RW
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
RW
?
RW
RESET
13.1 Hardware reset
?
?
?
?
00
16
00
16
?
?
0
0
0
00
16
0
0
0
0
0
0
?
?
00
16
00
16
?
?
00
16
00
16
?
?
00
16
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
?
?
?
1
0
0
0
b0
0
1
13–5
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