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b7
b6
b5
b4
b3
b2
Fig. 4.10.1 Structure of INT
b1
b0
INT
to INT
interrupt control registers (Addresses 7D
0
2
Bit
Interrupt priority level select bits
0
1
2
Interrupt request bit (Note)
3
4
Polarity select bit
Level sense/Edge sense select bit
5
7, 6
Nothing is assigned.
Note: The INT
to INT
0
___
(i=0 to 2) interrupt control register
i
7751 Group User's Manual
4.10 External interrupts (INT
Bit name
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : No interrupt request
1 : Interrupt request
0 : Set the interrupt request bit at
"H" level for level sense and at
falling edge for edge sense.
1 : Set the interrupt request bit at
"L" level for level sense and at
rising edge for edge sense.
0 : Edge sense
1 : Level sense
interrupt request bits are invalid when selecting the level sense.
2
INTERRUPTS
___
interrupt)
i
to 7F
)
16
16
Functions
At reset
0
Low level
0
0
High level
0
0
0
Undefined
RW
RW
RW
RW
RW
RW
RW
–
4–21
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