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UART0 transmit/receive mode register (Address 30
UART1 transmit/receive mode register (Address 38
b7
1
UART0 transmit/receive control register 0 (Address 34 )
UART1 transmit/receive control register 0 (Address 3C )
b7
0
Fig. 7.4.8 Initial setting example for relevant registers when receiving
7.4 Clock asynchronous serial I/O (UART) mode
)
16
)
16
b0
b2 b1 b0
1 0 0: UART mode (7 bits)
1 0 1: UART mode (8 bits)
1 1 0: UART mode (9 bits)
Internal/External clock select bit
0: Internal clock
1: External clock
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
Odd/Even parity select bit
0: Odd parity
1: Even parity
Parity enable bit
0: Parity disabled
1: Parity enabled
Sleep select bit
0: Sleep mode cleared (ignored)
1: Sleep mode selected
Note: Set the transfer data format in
the same way as set on the
transmitter side.
16
16
b0
BRG count source select bits
b1b0
0 0 : f
/f
2
4
0 1 : f
/f
16
32
1 0 : f
/f
64
128
1 1 : f
/f
512
1024
/
select bit
CTS
RTS
0 :
function selected (
CTS
RTS
function disabled)
1 :
function selected
RTS
7751 Group User's Manual
UART0 baud rate register (BRG0) (Address 31
UART1 baud rate register (BRG1) (Address 39
b7
b0
Port P8 direction register (Address 14
b7
b0
0
0
UART0 receive interrupt control register (Address 72
UART1 receive interrupt control register (Address 74
b7
b0
UART0 transmit/receive control register 1 (Address 35
UART1 transmit/receive control register 1 (Address 3D
b7
1
Reception starts when the start
bit is detected.
SERIAL I/O
)
16
)
16
Set to 00
to FF
.
16
16
)
16
RxD
pin
0
RxD
pin
1
)
16
)
16
Interrupt priority level select bits
When using interrupts, set these bits to
level 1–7.
When disabling interrupts, set these bits
to level 0.
)
16
)
16
b0
Receive enable bit
1: Reception enabled
7–47
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