Renesas 7700 FAMILY User Manual page 287

CONNECTION WITH EXTERNAL DEVICES
12.4 Hold function
<When inputting "L" level to
completed with 1-bus cycle>
State when inputting "L" level to
External data bus
Judgment timing of input
level to HOLD pin
Clock
ALE
R/W
External address bus /
External data bus
External address bus
BHE
HOLD
HLDA
When accepting a Hold request, not a new address but an address
output just before is output again.
Notes 1: This figure shows the case of 2 access in low-speed running.
2: Clock
3: This term indicated by Note 3 becomes 1.5 cycles in 5 access in high-speed
Fig. 12.4.3 Timing of acceptance of Hold request and termination of Hold state (2)
12–22
HOLD
Data length
8
Using
16
1
E
Address A
Data
(Note 3)
Term using bus
has the same polarity and the same frequency as
1
Signals timing to be input or output externally is ordained by clock
running. It is because the level judgment timing becomes the 1.5 cycles before the
end of the term using bus (See Table 12.4.2.)
7751 Group User's Manual
pin during term using bus; when data access is
pin
HOLD
External data bus width
8, 16
16
(Access from even address)
Floating
Address A
Floating
Floating
1
1
Hold state
Address B
1
1
Term using bus
.
BIU
as a basis.
1