Renesas 7700 FAMILY User Manual page 202

Transfer clock
"1"
Transmit enable bit
"0"
"1"
Transmit buffer
empty flag
"0"
"H"
CTS
i
"L"
T
ENDi
TxD
i
"1"
Transmit register
empty flag
"0"
"1"
UARTi transmit
interrupt request bit
"0"
The above timing diagram applies to
the following conditions:
Parity enabled
1 stop bit
CTS function selected
Fig. 7.4.6 Example of transmit timing when transfer data length is 8 bits (when parity enabled,
selecting 1 stop bit)
Transfer clock
"1"
Transmit enable bit
"0"
"1"
Transmit buffer
empty flag
"0"
T
ENDi
TxD
i
"1"
Transmit register
empty flag
"0"
"1"
UARTi transmit
interrupt request bit
"0"
The above timing diagram applies to
the following conditions:
Parity disabled
2 stop bits
CTS function disabled
Fig. 7.4.7 Example of transmit timing when transfer data length is 9 bits (when parity disabled,
selecting 2 stop bits)
7.4 Clock asynchronous serial I/O (UART) mode
Tc
Data is set in UARTi transmit buffer register.
Start bit Parity bit
ST D D D D D D D D
0 1 2 3 4 5 6
Cleared to "0" when interrupt request is accepted or cleared by software.
T : Next transmit conditions are examined when this signal level is "H."
ENDi
(T is an internal signal. Accordingly, it cannot be read from an external.)
ENDi
Tc: 16(n + 1)/fi or 16(n + 1)/f
Tc
Data is set in UARTi transmit buffer register.
Start bit
ST D D D D D D D
0 1 2 3 4 5 6
Cleared to "0" when interrupt request is accepted or cleared by software.
T : Next transmit conditions are examined when this signal level is "H."
ENDi
(T
ENDi
Tc: 16(n + 1)/fi or 16(n + 1)/f
7751 Group User's Manual
UARTi transmit register
UARTi transmit buffer register
Stopped because transmit enable bit = "0"
Stop bit
P SP ST D D D D D
7 0 1 2 3 4
EXT
fi: BRGi count source frequency (f /f
2
f : BRGi count source frequency (external clock)
EXT
n: Value set to BRGi
UARTi transmit register
Stopped because transmit enable bit = "0"
Stop bit Stop bit
D D SP SP ST D D D D
7 8 0 1 2 3
is an internal signal. Accordingly, it cannot be read from an external.)
EXT
fi: BRGi count source frequency (f
f : BRGi count source frequency (external clock)
EXT
n: Value set to BRGi
SERIAL I/O
ST
D D D P SP
5 6 7
, f /f , f /f , f /f )
4 16 32 64 128 512 1024
UARTi transmit buffer register
ST
D D D D D SP SP
4 5 6 7 8
/f , f /f , f /f , f /f )
2 4 16 32 64 128 512 1024
D D
0 1
D D
0 1
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