Processor Status Register (Ps) - Renesas 7700 FAMILY User Manual

CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit

2.1.9 Processor status register (PS)

The processor status register is an 11-bit register.
Figure 2.1.5 shows the structure of the processor status register.
b15 b14 b13 b12
0
0 0
Note: Fix bits 11–15 to "0."
Fig. 2.1.5 Processor status register structure
(1) Bit 0: Carry flag (C)
It retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic
operation. This flag is also affected by shift and rotate instructions. When the BCC or BCS instruction
is executed, this flag's contents determine whether the program causes a branch or not.
Use the SEC or SEP instruction to set this flag to "1," and use the CLC or CLP instruction to clear
it to "0."
(2) Bit 1: Zero flag (Z)
It is set to "1" when a result of an arithmetic operation or data transfer is "0," and cleared to "0" when
otherwise. When the BNE or BEQ instruction is executed, this flag's contents determine whether the
program causes a branch or not.
Use the SEP instruction to set this flag to "1," and use the CLP instruction to clear it to "0."
Note: This flag is invalid in the decimal mode addition (the ADC instruction).
(3) Bit 2: Interrupt disable flag (I)
It disables all maskable interrupts (interrupts other than watchdog timer, the BRK instruction, and
zero division). Interrupts are disabled when this flag is "1." When an interrupt request is accepted,
this flag is automatically set to "1" to avoid multiple interrupts. Use the SEI or SEP instruction to set
this flag to "1," and use the CLI or CLP instruction to clear it to "0." This flag is set to "1" at reset.
(4) Bit 3: Decimal mode flag (D)
It determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic
is performed when this flag is "0." When it is "1," decimal arithmetic is performed with each word
treated as two or four digits decimal (determined by the data length flag). Decimal adjust is automatically
performed. Decimal operation is possible only with the ADC and SBC instructions. Use the SEP
instruction to set this flag to "1," and use the CLP instruction to clear it to "0." This flag is cleared
to "0" at reset.
(5) Bit 4: Index register length flag (x)
It determines whether each of index register X and index register Y is used as a 16-bit register or
an 8-bit register. That register is used as a 16-bit register when this flag is "0," and as an 8-bit
register when it is "1." Use the SEP instruction to set this flag to "1," and use the CLP instruction
to clear it to "0." This flag is cleared to "0" at reset.
Note: When transferring data between registers which are different in bit length, the data is transferred
with the length of the destination register, but except for the TXA, TYA, TXB, TYB, and TXS
instructions. Refer to "7751 Series Software Manual" for details.
2–8
b11 b10 b9 b8
0 0 IPL
7751 Group User's Manual
b7 b6 b5 b4 b3
N
V m x D
b2 b1 b0
Processor status
C
I Z
register (PS)