Process On Detecting Error - Renesas 7700 FAMILY User Manual

7.4.7 Process on detecting error

Errors listed below can be detected in the UART mode:
Overrun error
An overrun error occurs when the next data is prepared in the UARTi receive register with the receive
completion flag = "1" (that is, data present in the UARTi receive buffer register) and that data is transferred
to the UARTi receive buffer register. In other words, when the next data is prepared before the contents
of the UARTi receive buffer register is read out, an overrun error occurs. When an overrun error occurs,
the next receive data is written into the UARTi receive buffer register, and the UARTi receive interrupt
request bit is not changed.
Framing error
A framing error occurs when the number of detected stop bits does not match the number of stop bits set.
(The UARTi interrupt request bit becomes "1.")
Parity error
A parity error occurs when the sum of "1"s in the parity bit and character bits does not match the number
of "1"s set. (The UARTi interrupt request bit becomes "1.")
Each error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer
register, and the corresponding error flag is set to "1." Furthermore, when any of the above errors occurs,
the error sum flag is set to "1." Accordingly, the error sum flag informs the user whether any error has
occurred or not.
The overrun error flag is cleared to "0" by clearing the receive enable bit to "0."
The framing error flag and the parity error flag are cleared to "0" by reading the contents of the UARTi
receive buffer register low-order byte or clearing the receive enable bit to "0." The error sum flag is cleared
to "0" by clearing the all error flags, which are overrun, framing, and parity.
When errors occur during reception, initialize the error flags and the UARTi receive buffer register, and
then perform reception again. When it is necessary to perform retransmission owing to an error which
occurs in the receiver side, set the UARTi transmit buffer register again, and then starts transmission
again.
The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer
register again are described below.
(1) Method of initializing UARTi receive buffer register
Clear the receive enable bit to "0" (reception disabled).
Set the receive enable bit to "1" again (reception enabled).
(2) Method of setting UARTi transmit buffer register again
Clear the serial I/O mode select bits to "000
Set the serial I/O mode select bits again.
Set the transmit enable bit to "1" (transmission enabled), and set the transmit data to the UARTi
transmit buffer register.
7.4 Clock asynchronous serial I/O (UART) mode
" (serial I/O ignored).
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7751 Group User's Manual
SERIAL I/O
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