Renesas 7700 FAMILY User Manual page 443

FLASH MEMORY VERSION
19.2 Serial input/output mode
Program command
Figure 19.2.3 shows the program command execution timing.
The command code "40
The low–order 8 bits and the high–order 8 bits of the address are input at the second and third
transfer.
The data is input at the forth transfer.
Programming is started at the last rising edge of the forth transfer serial clock and the BUSY signal
becomes "H" level. The input data is programmed to the specified address (input address) within
10 µs as measured by the built–in timer and the BUSY signal becomes "L" level. Programming is
performed by the byte unit.
Note: Be sure to execute a program verify command after executing the program command. If this
verification fails, execute repeatedly the program and program verify commands until the
verification passes. (Refer to "19.2.4 Program algorithm flow chart.")
SCLK
SDA 0 0 0 0 0
Command code input (40
"H"
OE
BUSY
Fig. 19.2.3 Program command execution timing
19–26
" is input at the first transfer.
16
t
CH
A
0
0 1 0
Program address input
)
16
(Low-order)
7751 Group User's Manual
t
CH
A A A
7 8 15
Program address input
(High-order)
t
CH
D D
0 7
Program data input
t
Program
t
PC
WP