Storing Registers - Renesas 7700 FAMILY User Manual

4.7 Sequence from acceptance of interrupt request to execution of interrupt routine

4.7.2 Storing registers

The register storing operation performed during INTACK sequence depends on whether the contents of the
stack pointer (S) at accepting interrupt request are even or odd.
When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the
processor status register (PS) are stored as a 16-bit unit simultaneously at each other. When the contents
of the stack pointer (S) are odd, they are stored with twice by an 8-bit unit for each. Figure 4.7.3 shows
the register storing operation.
In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and
processor status register (PS) are stored to the stack area. The other necessary registers must be stored
by software at the beginning of the interrupt routine.
Using the PSH instruction can store all CPU registers except the stack pointer (S).
(1) Content of stack pointer (S) is even
Address
[S] – 5 (odd)
[S] – 4 (even)
[S] – 3 (odd)
[S] – 2 (even)
[S] – 1 (odd)
[S] (even)
(2) Content of stack pointer (S) is odd
Address
[S] – 5 (even)
[S] – 4 (odd)
[S] – 3 (even)
[S] – 2 (odd)
[S] – 1 (even)
[S] (odd)
[S] is an initial value that the stack pointer (S) indicates at accepting an interrupt
request. The S's contents become [S] – 5 after storing the above registers.
Fig. 4.7.3 Register storing operation
Low-order byte of processor status register (PS
High-order byte of processor status register (PS
Low-order byte of program counter (PC
High-order byte of program counter (PC
Program bank register (PG)
Low-order byte of processor status register (PS
High-order byte of processor status register (PS
Low-order byte of program counter (PC
High-order byte of program counter (PC
Program bank register (PG)
7751 Group User's Manual
Storing order
)
L
Stores 16 bits at a time.
)
H
)
L
Stores 16 bits at a time.
)
H
Storing is completed with 3 times.
Storing order
)
L
)
H
)
L
)
H
Storing is completed with 5 times.
INTERRUPTS
Stores by each 8 bits.
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