A-D Conversion Method (Successive Approximation Conversion Method) - Renesas 7700 FAMILY User Manual

Mitsubishi 16-bit single-chip microcomputer
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A-D CONVERTER

8.3 A-D conversion method (successive approximation conversion method)

8.3 A-D conversion method (successive approximation conversion method)
The A-D converter compares the comparison voltage (V
contents of the successive approximation register, with the analog input voltage (V
the analog input pin (AN
is converted into a digital value. When a trigger is generated, the A-D converter performs the following
processing:
Determining bit 9 of the successive approximation register
The A-D converter compares V
register are "1000000000
Bit 9 of the successive approximation register changes according to the comparison result as follows:
When V
< V
ref
IN
When V
> V
ref
IN
Determining bit 8 of the successive approximation register
After setting bit 8 of the successive approximation register to "1," the A-D converter compares V
with V
. Bit 8 changes according to the comparison result as follows:
IN
When V
< V
ref
IN
When V
> V
ref
IN
Determining bits 7 to 0 of the successive approximation register
Operation in
Operation in
When the LSB is determined, the contents (conversion result) of the successive approximation register
are transferred to the A-D register i.
The comparison voltage (V
register. Table 8.3.1 lists the relationship between the successive approximation register's contents and V
Table 8.3.2 and Table 8.3.3 list changes of the successive approximation register and V
conversion. Figure 8.3.1 shows the ideal A-D conversion characteristics in the 10-bit mode.
Table 8.3.1 Relationship between successive approximation register's contents and V
Successive approximation register's contents: n
V
: Reference voltage
REF
8–10
). By reflecting the comparison result on the successive approximation register, V
i
with V
ref
" (initial value).
2
, bit 9 = "1"
, bit 9 = "0"
, bit 8 = "1"
, bit 8 = "0"
are performed for bits 7 to 0 in the 10-bit mode.
are performed for bits 7 to 2 in the 8-bit mode.
) is generated according to the latest contents of the successive approximation
ref
0
1 to 1023
7751 Group User's Manual
), which is internally generated according to the
ref
. At this point, the contents of the successive approximation
IN
), which is input from
IN
during the A-D
ref
V
(V)
ref
0
V
REF
(n – 0.5)
1024
IN
ref
.
ref
ref

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