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CONNECTION WITH EXTERNAL DEVICES
12.4 Hold function
Table 12.4.2 Judgment timing of input level of HOLD pin during used bus
Low-speed running [ f (X
Internal area access
(Note)
2 access in low-speed running
Judgment timing of input
level to HOLD pin
Clock
1
BIU
E
ALE
Reading
A
Writing
A W
Note : Signals when accessing an internal area means signals which are output from pins
externally when accessing an internal area in the memory expansion mode.
A: Address
R: Data to be read
12–20
) ≤ 25 MHz ]
IN
External area access
2 access in low-speed running
Judgment timing of input
level to HOLD pin
Clock
1
BIU
E
ALE
Reading
A
R
Writing
A W
3 access in low-speed running
Judgment timing of input
level to HOLD pin
Clock
1
BIU
E
ALE
Reading
A
R
Writing
A
W
4 access in low-speed running
Judgment timing of input
level to HOLD pin
Clock
1
BIU
E
ALE
A
R
Reading
A
W
Writing
W: Data to be written
?: Undefined value
7751 Group User's Manual
_____
High-speed running [ f (X
Internal area access
(Note)
2 access in high-speed running
(RAM)
Judgment timing of input
level to HOLD pin
Clock
1
BIU
E
ALE
Reading
A
Writing
A
?
3 access in high-speed running
(ROM, SFR)
Judgment timing of input
level to HOLD pin
Clock
1
BIU
E
ALE
Reading
A
Writing
A
W
) ≤ 40 MHz ]
IN
External area access
3 access in high-speed running
Judgment timing of input
level to HOLD pin
Clock
1
BIU
E
ALE
Reading
A
R
Writing
A
W
4 access in high-speed running
Judgment timing of input
level to HOLD pin
Clock
1
BIU
E
ALE
Reading
A
A
R
R
Writing
A
A
W
W
5 access in high-speed running
Judgment timing of input
level to HOLD pin
Clock
1
BIU
E
ALE
Reading
Reading
A
A
Writing
Writing
A
A
W
W
R
R
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