[Precautions When Operating In Single-Chip Mode] - Renesas 7700 FAMILY User Manual

CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes

[Precautions when operating in single-chip mode]

The bus cycle select bits (bits 4 and 5 at address 5F
not make those bits state of not selected in all cases. Especially in low-speed running, rewrite both bits
at the same time to "01
b7 b6 b5 b4 b3 b2 b1
0 0 0 0
Fig. 2.5.5 Structure of processor mode register 1
2–28
," "10 " or "11 ." These bits are cleared to "00
2 2 2
b0
Processor mode register 1 (Address 5F
Bit Bit name
1, 0
Fix these bits to "0."
Clock source for peripheral
2
devices select bit
CPU running speed select bit
3
Bus cycle select bits
4
5
Fix these bits to "0."
7, 6
Note: Fix this bit to "0" when f(X
7751 Group User's Manual
) is not used in the single-chip mode. However, do
16
" at reset.
2
)
16
Functions
0 : divided by 2
(Note)
1 :
0 : High-speed running
1 : Low-speed running
(Note)
In high-speed running
b5 b4
0 0 : 5 access in high-speed running
0 1 : 4 access in high-speed running
1 0 : 3 access in high-speed running
1 1 : Not selected
In low-speed running
b5 b4
0 0 : Not selected
0 1 : 4 access in low-speed running
1 0 : 3 access in low-speed running
1 1 : 2 access in low-speed running
) > 25 MHz.
IN
RW
At reset
0 RW
RW
0
0 RW
0 RW
0
RW
RW
0