Renesas 7700 FAMILY User Manual page 64

Table 4.3.1 Setting of interrupt priority level
Interrupt priority level select bits
b1
b2
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
Table 4.3.2 Interrupt enabled level corresponding to IPL contents
IPL IPL
2 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
IPL : Bit 8 in processor status register (PS)
0
IPL : Bit 9 in processor status register (PS)
1
IPL : Bit 10 in processor status register (PS)
2
b0
0
Level 0 (Interrupt disabled)
1
Level 1
0
Level 2
1
Level 3
0 Level 4
1
Level 5
0
Level 6
1
Level 7
IPL
0
0 Enable level 1 and above interrupts.
1 Enable level 2 and above interrupts.
0 Enable level 3 and above interrupts.
1 Enable level 4 and above interrupts.
0 Enable level 5 and above interrupts.
1 Enable level 6 and level 7 interrupts.
0 Enable only level 7 interrupt.
1 Disable all maskable interrupts.
7751 Group User's Manual
Interrupt priority level
Enabled interrupt priority level
INTERRUPTS
4.3 Interrupt control
Priority
—
Low
High
4–9