Renesas 7700 FAMILY User Manual page 106

(1) Switching between up-count and down-count
The up-down register (address 44
count from and to the down-count. This switching is performed by the up-down bit when the up-down
switching factor select bit (bit 4 at addresses 56
TAi pin when the up-down switching factor select bit is "1."
OUT
When switching the up-count/down-count, this switching is actually performed when the count source's
next valid edge is input.
Switching by up-down bit
The counter down-counts when the up-down bit is "0," and up-counts when the up-down bit is "1."
Figure 5.4.5 shows the structure of the up-down register.
Switching by TAi
The counter down-counts when the TAi
TAi pin's input signal is at "H" level.
OUT
When using the TAi
direction registers' bits which correspond to the TAi
b7 b6 b5 b4 b3 b2
Fig. 5.4.5 Structure of up-down register
) or the input signal from the TAi
16
pin's input signal
OUT
pin input signal to switch the up-count/down-count, set the port P5 and P6
OUT
b1 b0
Up-down register (Address 44
Bit
Timer A0 up-down bit
0
1 Timer A1 up-down bit
2
Timer A2 up-down bit
3 Timer A3 up-down bit
Timer A4 up-down bit
4
5
Timer A2 two-phase pulse signal
processing select bit
6 Timer A3 two-phase pulse signal
processing select bit
Timer A4 two-phase pulse signal
7
processing select bit
Note: Use the LDM or STA instruction when writing to bits 5 to 7.
7751 Group User's Manual
to 5A ) is "0," and by the input signal from the
16 16
pin's input signal is at "L" level, and up-counts when the
OUT
pin for the input mode.
OUT
)
16
Bit name
0 : Down-count
1 : Up-count
This function is valid when the
contents of the up-down register are
selected as the up-down switching
factor.
0 : Disabled Two-phase pulse signal
processing function
(Note)
1 : Enabled Two-phase pulse signal
processing function
(Note)
When not using the two-phase pulse
signal processing function, make
sure to set the bit to "0."
(Note)
The value is "0" at reading.
TIMER A
5.4 Event counter mode
pin is used to switch the up-
OUT
Functions
At reset
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
WO
WO
WO
5–25